Ofotsu MacCarthy
2012-03-27 21:24:06 UTC
For A5Q1, do we assume each instruction takes 1 clock cycle (and account
for loads and branches where necessary) or do we follow the pipeline
diagram where it takes 5 clock cycles to go through the instruction and
the next instruction begins on the 2nd clock cycle.
for loads and branches where necessary) or do we follow the pipeline
diagram where it takes 5 clock cycles to go through the instruction and
the next instruction begins on the 2nd clock cycle.